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Method using multiple layer annealing cap for fabricating group III-nitride semiconductor device structures and devices formed thereby

Patent image
CCDC ARL

A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor.

Inventors: 
Hager IV, Carl Emmett; Derenge, Michael Andrew; Jones, Kenneth Andrew
Patent Number: 
Technical domain: 
Materials and Coatings
FIle Date: 
2008-12-03
Grant Date: 
2011-07-12
Grant time: 
951 days
Grant time percentile rank: 
17
Claim count percentile rank: 
6
Citations percentile rank: 
2
'Cited by' percentile rank: 
1
Assignee: 
US ARMY