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Hetero-junction tunneling transistor

Patent image
CCDC ARL

A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that a portion of the second layer overlies the first layer and forms the drain for the transistor. An insulating layer and metallic gate for the transistor is deposited on top of the second layer so that the gate is aligned with the overlying portions of the first and second layers. The gate voltage controls the conduction between the source and the drain and the conduction between the first and second layers occurs by vertical tunneling between the layers.

Inventors: 
Nayfeh, Osama M.; Dubey, Madan
Patent Number: 
Technical domain: 
Materials and Coatings
FIle Date: 
2012-05-24
Grant Date: 
2014-01-14
Grant time: 
600 days
Grant time percentile rank: 
10
Claim count percentile rank: 
3
Citations percentile rank: 
1
'Cited by' percentile rank: 
1
Assignee: 
US ARMY